2014 Rice Oil & Gas HPC

Emerging memory technologies like Phase Change Memory or Memristors (generically called SCM or Storage Class Memory) combine the ability to access data at byte granularity with the persistence of storage devices like hard disks or SSDs. With SCM, application developers can focus on a single storage abstraction rather than having to deal with both byte/word-grained accesses to DRAM locations and block-based accesses to file/disk ranges. By accessing data directly from SCM addresses instead of slow block I/O operations, developers can gain 1-2 orders of performance. However, this unification of storage into a single directly accessed persistent storage memory tier is a mixed blessing, as it pushes upon developers the burden of ensuring that SCM stores are ordered correctly, flushed from processor caches, and if interrupted by sudden machine stoppage, do not leave objects in SCM in inconsistent states. The complexity of ensuring properly ordered and all-or-nothing updates raises significant reliability and programmability challenges. We propose a solution called Write Aside Persistence, or WrAP, that provides durability and consistency for SCM writes, while ensuring fast paths to data in processor caches, DRAM, and persistent memory tiers. WrAP is presented in a software / hardware architecture and also as a software only approach. Simulations of transactional data structures, such as the Graph 500 Benchmark and Standard Template Library tests, indicate the potential for significant performance gains using Write Aside Persistence for atomic and durable writes to Storage Class Memory.